Summit Design, Inc. Visual HDL for VHDL 5.0

Visual HDL for VHDL 5.0
The Standard for Next Generation Design Entry

Visual HDL for VHDL is a graphical entry and verification solution designed to simplify and accelerate top-down design. Visual HDL can raise productivity by allowing system level, behavioral level and functional level design entry using graphical design methods such as block diagrams, state machines, flow charts and truth tables.

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Visual HDL for VHDL.
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As a result, engineers no longer need to textually program their designs in lines of VHDL code. Once the design is graphically captured, Visual HDL can then automatically generate synthesizable HDL code that is optimized for specific synthesis tools.

Benefits
Visual HDL uses VHDL as its internal data format, allowing the product to support all the hardware modeling features of this standard HDL language. The Visual HDL design environment offers several benefits to top-down designers, including: easier design entry, verification and reuse, and faster, more complete design debugging. Because Visual HDL represents HDL code graphically, designers can better communicate their ideas in a much more intuitive manner. This allows experienced and novice HDL designers to work together efficiently. Visual HDL automatically generates HDL code that is optimized for efficient synthesis. It can also import VHDL code and automatically generate graphics from the source HDL. Utilizing the graphical representations generated by Visual HDL, designers are able to quickly determine the original design intent, allowing them to save time by reusing design components in future designs.

Graphical Simulation and Debug Environment
An important aspect of Visual HDL is its graphical simulation and debug environment. This environment allows designers to view the path of simulation execution and the simulation results. This gives them the opportunity to shorten development time by focusing on debugging their circuits instead of debugging their HDL code. Visual HDL also provides point-and-click functionality which allows engineers to quickly determine the cause of a bug by highlighting the specific line of text and the related graphical representation where the error exists, thereby significantly shortening the time to debug a program.

What's New in 5.0
Visual HDL 5.0, the leading systems level design automation (SLDA) software tool for increasing design productivity, provides many new and exciting features. These include: improved synthesis scripting, hardware description language (HDL) code generation and graphical editing capabilities. Visual HDL 5.0 also provides support for FureAtria's ClearCase configuration-management (CM) and a link to their version-control software.

Text-To-Graphics Option
Text-To-Graphics is now offered as an add-on. With Text-To-Graphics, the user can convert any VHDL or Verilog textual description into graphics and control the process by choosing the resultant graphical format. Text-To-Block-Diagram now contains the graphic bundling feature (as described below). Text-To-State Machine converts VHDL/Verilog descriptions into graphical State Diagrams, and the Text-To-Flow Chart feature converts textual descriptions of VHDL and Verilog into graphical flowcharts.

Other Text-To-Graphics Features

Ability to edit symbol instances created in Block Diagrams by Block to Component or VHDL to Block Diagram.

The ability to put priorities on transitions after Text-To-Graphics.

Cause and Effect link from generated graphics back to textual HDL source.

Cross reference on connectors during VHDL to Block Diagram.

Graphic Bundling (during Text-To-Block-Diagram); the user can define a special directive file to group individual scaler signals into bundles, so the resultant graphics are more readable.

The Lastest Editor Features
Visual HDL now offers expanded graphical editing capabilities with user-defined templates, Japanese Kanji fonts (both on PC and UNIX), group edit commands, and global update of the entire design tree.

Users of Visual HDL 5.0 have access to all CM features and functionality currently available in Visual HDL through RCS. In addition Visual HDL 5.0 now has expanded Version Control capabilities which include the following; RCS keyword support and External Version Control. All side objects are now kept under Version Control.

This latest version of Visual HDL's code generation capabilities feature has enhanced static and synthesis checks, support for Verilog CaseX and CaseZ, Uselib and Ifdef statements, support for VHDL configurations declarations, and improved junction state support and automatic default assignments for asychronous outputs to avoid inferred latches.

Additional Graphic Editor Features

Ability to add "bus" and "register" to signals.
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Query Select-allows user to select all graphic elements in design units based upon predefined criteria.
Array-Comment field in Declaration and Interface Forms.
Additional Global Data Information--full information of states and transitions now added to the global data display.
Global Search--string finding capabilities have been expanded along with Global Search and Replace.

Automatic Synthesis Scripting
Visual HDL 5.0 also allows the user to automatically generate synthesis shell scripts based on the design information, user defined templates, and the targeted synthesis vendor.

Simulation Comparison
Designers can now compare simulation results with previsous simulation runs or with expected outputs.

Synopsys Behavioral Compiler Support
Version 5.0 of Visual HDL for VHDL generates code that is optimized for Synopsys' Behavioral Compiler tool.

Visual HDL supports a broad range of synthesis and simulation products, including products from Synopsys, Mentor Graphics, Cadence, VIEWlogic, Compass, IBM, Altera, Synplicity and Exemplar.

Visual HDL for VHDL supports Windows-based PCs and UNIX workstations.